1. Field of the Invention
The present invention relates to a semiconductor device, and especially relates to a semiconductor device that generates an internal clock signal using a DLL (Delay-Locked Loop) circuit.
2. Description of Related Art
In the recent years, semiconductor devices that perform operations in synchronization with clocks are widely used. For example, a DDR (Double Data Rate) type synchronous memory used as a main memory in a personal computer, etc. In such a semiconductor device, since there is a need to synchronize an output timing of read data to an external clock signal, a DLL circuit generating an internal clock signal in synchronization with the external clock signal is used. Japanese Patent Application Laid-Open No. 2001-332086 discloses an example of such a DLL circuit.
The DLL circuit is configured by including a delay circuit to generate the internal clock signal by delaying the external clock signal. The internal clock signal is transmitted to an output buffer to output the read data via a clock transmission circuit. The output buffer outputs the read data at the timing in synchronization with the internal clock signal that has been supplied as aforementioned.
Here, the internal clock signal is delayed during the transmission from the DLL circuit to the output buffer, and is further delayed inside the output buffer. Thus, in order to accurately synchronize the output timing of the read data with the external clock signal, the DLL circuit needs to generate the internal clock signal taking these delays into account. In order to do so, in the DLL circuit, a replica circuit that assimilates to the transmission path from the DLL circuit to the output buffer and the output buffer is used.
The replica circuit gives the same delay amount as those in the actual circuits (the transmission path from the DLL circuit to the output buffer and the output buffer) to the internal clock signal, and outputs the same as a feedback clock signal. The DLL circuit adjusts the delay amount in the delay circuit such that a rising phase of the feedback clock signal coincides with a rising phase of the external clock signal, and a duty ratio of the feedback clock signal is at a predetermined value (normally 50%). Due to this, the synchronization of the output timing of the read data with the external clock signal is realized.
In the recent years, acceleration in operation speed of the semiconductor devices has further progressed, and a permissible amount of an offset of the output timing of the read data is becoming small. Especially in regards to the duty ratio, even a subtle offset of 10 psec to 20 psec can no longer be permitted.
However, there is a limit of accuracy of the DLL circuit, and it has become difficult to cope with such acceleration as the years go by. As one reason of the limit of accuracy of the DLL circuit, a limit of accuracy in the replica circuit can be mentioned. The replica circuit is a circuit that assimilates to the transmission path from the DLL circuit to the output buffer and the output buffer as aforementioned, however, it is no more than a replica and is not the same as the actual circuits, so a feedback clock signal that is completely in synchronization with the output timing of the read data cannot be generated. Conventionally, improvements has somehow been made to the accuracy of the replica circuit by fine adjustments of the replica circuit in a testing stage, however, the improvement in accuracy of the replica circuit by the fine adjustment is almost at its limit, and a drastic improvement is being required.